Applied Materials Accelerates AI and HPC Manufacturing

Applied Materials has announced a suite of next-generation chip manufacturing solutions—Kinex™, Xtera™, and PROVision™—targeting critical stages from advanced packaging to epitaxy and metrology. The new technologies aim to enhance the performance, power efficiency, and yield of chips for AI and high-performance computing (HPC) applications.

The company introduced the industry’s first integrated die-to-wafer hybrid bonding system, combining pre-clean, alignment, bonding, and in-situ metrology within a single platform. This innovation enables ultra-precise alignment, reduced interconnect pitch, and improved process consistency. Featuring die-tracking and overlay drift detection, the system achieves higher yield and reliability—ideal for high-density heterogeneous integration such as GPUs, HPC, and high-bandwidth memory (HBM). Developed jointly with Besi, the technology is currently under evaluation by logic, memory, and OSAT customers.

For advanced logic nodes at 2nm and below, Applied Materials has developed a “deposition-etch” co-optimization process that addresses the challenges of filling high aspect ratio source/drain trenches in gate-all-around (GAA) transistors. The new process dynamically adjusts opening dimensions during material growth, achieving void-free, uniform structures. Compared with conventional methods, it reduces gas usage by around 50% and improves within-die uniformity by more than 40%, enhancing device performance and reliability.

Applied also introduced the PROVision™ eBeam metrology system, the industry’s first high-throughput platform featuring cold field emission (CFE) technology. The new system delivers up to 50% higher imaging resolution and 10× faster throughput, enabling sub-nanometer 3D imaging and multi-layer metrology for accurate on-device overlay and critical dimension (CD) measurements—helping fabs achieve tighter process control and higher productivity.

Source: China Times